During fabrication of flash memory arrays, such as flash memory arrays that include memory cells capable of storing two independent bits in separate locations within the memory cell (e.g., Advanced Micro Devices' (AMD) MirrorBit™ memory cells), bitlines are implanted in the substrate and an ONO (Oxide-Nitride-Oxide) stack is typically formed over the substrate. In the conventional flash memory array fabrication process, a layer of polycrystalline silicon (polysilicon) is typically deposited and lithographically patterned over the ONO stack to form a desired number of wordlines, which are situated over and aligned perpendicular to the bitlines. In the conventional flash memory array fabrication process, wordline critical dimension (i.e. wordline width) is determined by the lithographical patterning process. However, as the flash memory array is scaled down, the difficulty in forming wordlines having uniform wordline width increases significantly.
Additionally, during memory cell programming in a conventional flash memory array, a parasitic current can flow in a portion of the substrate situated between adjacent wordlines at or close to the interface between the bottom oxide layer in the ONO stack. This parasitic current, which is inversely proportional to the thickness of the ONO stack, can undesirably increase memory array power consumption and cause undesirable memory cell threshold voltage distribution in the memory array, which can reduce memory array performance and reliability.
Thus, there is a need in the art for a method of fabricating a flash memory array having reduced parasitic current flow in substrate portions situated between wordlines and having increased wordline critical dimension uniformity.